ARM Research Summit & GEM5 Workshop 2017 — Cambridge, UK
We explain how GEM5 enabled us to develop a target-agnostic JIT compiler, in which no knowledge about the target ISA is coded by the human programmer; instead, the backend is inferred, using logic programming, from a formal machine description written in a Processor Description Language. Debugging such a JIT presents some challenges which can not be addressed using traditional approaches. One such challenge is the impedance mismatch between the high-level abstractions in the PDL and the low-level inferred implementation. In this talk, we present a new debugger based on simulating the execution of the target runtime VM in GEM5; the debugger frontend connects to this simulation using the RSP wire protocol.