Smalltalks-2018 & the Bee VM Hackathon


Travels with RISC-V

Author: Boris Shingarov
Affiliation: LabWare
Conference: 12th Smalltalks Conference, Salta, 2018

Abstract:

The free instruction set RISC-V, which has reached the momentum to be the clear candidate for the defining ISA of the next decade, presents a number of unique opportunities for Smalltalk. One, there is a vacuum for dynamic runtimes. Two, there is a shift in design objectives accepted by the community. For example, whereas we used to be content with intuitive suggestions for why a particular sequence of CPU instructions may work, today's customers demand formal verification of their whole software/hardware stacks. The definition of "performance" is undergoing equally large changes.

Two experimental Smalltalk VMs -- TAM and VLS -- are designed to enable exploration of these challenges. This talk presents these VMs running on real RISC-V hardware, yielding a number of unexpected differences with the more conventional CPUs.


Photos

The Conference

The Organ Crawl

Salta and Buenos Aires