Smalltalks-2018 & the Bee VM Hackathon

Travels with RISC-V

Author: Boris Shingarov
Affiliation: LabWare
Conference: 12th Smalltalks Conference, Salta, 2018


The free instruction set RISC-V, which has reached the momentum to be the clear candidate for the defining ISA of the next decade, presents a number of unique opportunities for Smalltalk. One, there is a vacuum for dynamic runtimes. Two, there is a shift in design objectives accepted by the community. For example, whereas we used to be content with intuitive suggestions for why a particular sequence of CPU instructions may work, today's customers demand formal verification of their whole software/hardware stacks. The definition of "performance" is undergoing equally large changes.

Two experimental Smalltalk VMs -- TAM and VLS -- are designed to enable exploration of these challenges. This talk presents these VMs running on real RISC-V hardware, yielding a number of unexpected differences with the more conventional CPUs.

Category: Virtual Machine

CCS Concepts:

  • Software and its engineering - Virtual machines
  • Software and its engineering - Formal software verication
  • Programming languages - Processors


  • Virtual machine
  • Certied compilation
  • Program proof
  • Coq theorem prover
  • Curry–Howard correspondence
  • Processor Description Language
  • Retargetable compiler
  • GEM5
  • GDB Remote Serial Protocol

Photo courtesy Esteban Maringolo

As always, FAST issues nice certificates of attendance.


Smalltalks-2018 Conference

Bee VM Hackathon

The Organ Crawl: Cavaillé-Coll/Mutin,

The Organ Crawl: Forster & Andrews, 1882

Salta and Buenos Aires

Dedicated to Smalltalks?

Ok this is totally hilarious. The FedEx mailman just knocked on my door, brought me a copy of the Green Book (Krasner). Well I *hoped* it's the Green Book. What I got in the package, is a re-print and an incredibly weird one:

The First International Cuis Sprint, Buenos Aires, March 2019